Handbook of 3D Integration: 3D Process Technology	1
	Contents	7
	List of Contributors	19
	1 3D IC Integration Since 2008	25
	1.1 3D IC Nomenclature	25
	1.2 Process Standardization	26
	1.3 The Introduction of Interposers (2.5D)	28
	1.4 The Foundries	30
	1.4.1 TSMC	30
	1.4.2 UMC	31
	1.4.3 GlobalFoundries	31
	1.5 Memory	31
	1.5.1 Samsung	31
	1.5.2 Micron	32
	1.5.3 Hynix	33
	1.6 The Assembly and Test Houses	33
	1.7 3D IC Application Roadmaps	34
	References	35
	2 Key Applications and Market Trends for 3D Integration and Interposer Technologies	37
	2.1 Introduction	37
	2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing	40
	2.3 3D Integration-Focused Activities – The Global IP Landscape	42
	2.4 Applications, Technology, and Market Trends	46
	References	56
	3 Economic Drivers and Impediments for 2.5D/3D Integration	57
	3.1 3D Performance Advantages	57
	3.2 The Economics of Scaling	57
	3.3 The Cost of Future Scaling	58
	3.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction	61
	3.4.1 Required Economics for Interposer Use in Mobile Products	62
	3.4.2 Silicon Interposer Pricing	62
	References	64
	4 Interposer Technology	65
	4.1 Definition of 2.5D Interposers	65
	4.2 Interposer Drivers and Need	66
	4.3 Comparison of Interposer Materials	68
	4.4 Silicon Interposers with TSV	69
	4.5 Lower Cost Interposers	72
	4.5.1 Glass Interposers	72
	4.5.1.1 Challenges in Glass Interposers	73
	4.5.1.2 Small-Pitch Through-Package Via Hole Formation and Ultrathin Glass Handling	73
	4.5.1.3 Metallization of Glass TPV	75
	4.5.1.4 Reliability of Copper TPVs in Glass Interposers	76
	4.5.1.5 Thermal Dissipation of Glass	77
	4.5.1.6 Glass Interposer Fabrication with TPV and RDL	77
	4.5.2 Low-CTE Organic Interposers	77
	4.5.3 Polycrystalline Silicon Interposer	79
	4.5.3.1 Polycrystalline Silicon Interposer Fabrication Process	80
	4.6 Interposer Technical and Manufacturing Challenges	81
	4.7 Interposer Application Examples	82
	4.8 Conclusions	84
	References	85
	5 TSV Formation Overview	89
	5.1 Introduction	89
	5.2 TSV Process Approaches	91
	5.2.1 TSV-Middle Approach	92
	5.2.2 Backside TSV-Last Approach	92
	5.2.3 Front-Side TSV-Last Approach	93
	5.3 TSV Fabrication Steps	94
	5.3.1 TSV Etching	94
	5.3.2 TSV Insulation	95
	5.3.3 TSV Metallization	95
	5.3.4 Overburden Removal by CMP	96
	5.3.5 TSV Anneal	97
	5.3.6 Temporary Carrier Wafer Bonding and Debonding	98
	5.3.7 Wafer Thinning and TSV Reveal	98
	5.4 Yield and Reliability	99
	References	100
	6 TSV Unit Processes and Integration	103
	6.1 Introduction	103
	6.2 TSV Process Overview	104
	6.3 TSV Unit Processes	106
	6.3.1 Etching	106
	6.3.2 Insulator Deposition with CVD	107
	6.3.3 Metal Liner/Barrier Deposition with PVD	108
	6.3.4 Via Filling by ECD of Copper	108
	6.3.5 CMP of Copper	109
	6.3.6 Temporary Bonding between Carrier and Device Wafer	110
	6.3.7 Wafer Backside Thinning	110
	6.3.8 Backside RDL	111
	6.3.9 Metrology, Inspection, and Defect Review	111
	6.4 Integration and Co-optimization of Unit Processes in Via Formation Sequence	112
	6.5 Co-optimization of Unit Processes in Backside Processing and Via-Reveal Flow	113
	6.6 Integration and Co-optimization of Unit Processes in Via-Last Flow	115
	6.7 Integration with Packaging	116
	6.8 Electrical Characterization of TSVs	116
	6.9 Conclusions	120
	References	121
	7 TSV Formation at ASET	123
	7.1 Introduction	123
	7.2 Via-Last TSV for Both D2D and W2W Processes in ASET	127
	7.3 TSV Process for D2D	129
	7.3.1 Front-Side Bump Forming	130
	7.3.2 Attach WSS and Thinning	130
	7.3.3 Deep Si Etching from the Backside	131
	7.3.4 Liner Deposition	131
	7.3.5 Removal of SiO2 at the Bottom of Via	131
	7.3.6 Barrier Metal and Seed Layer Deposition by PVD	134
	7.3.7 Cu Electroplating	134
	7.3.8 CMP	134
	7.3.9 Backside Bump	135
	7.3.10 Detach WSS	135
	7.3.11 Dicing	136
	7.4 TSV Process for W2W	137
	7.4.1 Polymer Layer Coat and Development	138
	7.4.2 Barrier Metal and Seed Layer Deposition	138
	7.4.3 Cu Plating	138
	7.4.4 CMP	139
	7.4.5 First W2W Stacking (Face to Face)	140
	7.4.6 Wafer Thinning and Deep Si Etching	140
	7.4.7 TSV Liner Deposition and SiO2 Etching of Via Bottom	141
	7.4.8 Barrier Metal and Seed Layer Deposition and Cu Plating	141
	7.4.9 CMP	141
	7.4.10 Next W2W Stacking	142
	7.5 Conclusions	143
	References	143
	8 Laser-Assisted Wafer Processing: New Perspectives in Through-Substrate Via Drilling and Redistribution Layer Deposition	145
	8.1 Introduction	145
	8.2 Laser Drilling of TSVs	145
	8.2.1 Cost of Ownership Comparison	145
	8.2.2 Requirements for an Industrial TSV Laser Driller	147
	8.2.3 Drilling Strategy	148
	8.2.3.1 Mechanical	148
	8.2.3.2 Optical	149
	8.2.4 Experimental Drilling Results	150
	8.3 Direct-Write Deposition of Redistribution Layers	150
	8.3.1 Introduction on Redistribution Layers	150
	8.3.2 Direct-Write Characteristics	151
	8.3.3 Direct-Write Laser-Induced Forward Transfer	152
	8.3.4 LIFT Results	154
	8.4 Conclusions and Outlook	155
	References	156
	9 Temporary Bonding Material Requirements	159
	9.1 Introduction	159
	9.2 Technology Options	160
	9.2.1 Tapes and Waxes	160
	9.2.2 Chemical Debonding	160
	9.2.3 Thermoplastic Bonding Material and Slide Debonding	160
	9.2.4 Debonding Using Release Layers	161
	9.3 Requirements of a Temporary Bonding Material	162
	9.4 Considerations for Successful Processing	163
	9.4.1 Application of the Temporary Bonding Adhesive to the Device Wafer and Bonding to Carrier	163
	9.4.2 Moisture and Contaminants on Surface	163
	9.4.3 Total Thickness Variation	164
	9.4.4 Squeeze Out	164
	9.5 Surviving the Backside Process	165
	9.5.1 Edge Trimming	166
	9.5.2 Edge Cleaning	166
	9.5.3 Temperature Excursions in Plasma Processes	167
	9.5.4 Wafer Warpage due to CTE Mismatch	167
	9.6 Debonding	168
	9.6.1 Debonding Parameters in Slide-Off Debonding	168
	9.6.2 Mechanical Damage to Interconnects	168
	References	169
	10 Temporary Bonding and Debonding – An Update on Materials and Methods	171
	10.1 Introduction	171
	10.2 Carrier Selection for Temporary Bonding	172
	10.3 Selection of Temporary Bonding Adhesives	175
	10.4 Bonding and Debonding Processes	176
	10.5 Equipment and Process Integration	179
	References	180
	11 ZoneBOND®: Recent Developments in Temporary Bonding and Room-Temperature Debonding	183
	11.1 Introduction	183
	11.2 Thin Wafer Processing	183
	11.2.1 Thin Wafer Total Thickness Variation	185
	11.2.2 Wafer Alignment	187
	11.3 ZoneBOND Room-Temperature Debonding	187
	11.4 Conclusions	189
	References	190
	12 Temporary Bonding and Debonding at TOK	191
	12.1 Introduction	191
	12.2 Zero Newton Technology	192
	12.2.1 The Wafer Bonder	192
	12.2.2 The Wafer Debonder	194
	12.2.3 The Wafer Bonder and Debonder Equipment Lineups	194
	12.2.4 Adhesives	194
	12.2.5 Integration Process Performance	196
	12.3 Conclusions	198
	References	198
	13 The 3M™ Wafer Support System (WSS)	199
	13.1 Introduction	199
	13.2 System Description	199
	13.3 General Advantages	201
	13.4 High-Temperature Material Solutions	202
	13.5 Process Considerations	204
	13.5.1 Wafer and Adhesive Delamination	204
	13.5.2 LTHC Glass Delamination	205
	13.6 Future Directions	205
	13.6.1 Thermal Stability	205
	13.6.2 Elimination of Adhesion Control Agents	206
	13.6.3 Laser-Free Release Layer	207
	13.7 Summary	207
	Reference	208
	14 Comparison of Temporary Bonding and Debonding Process Flows	209
	14.1 Introduction	209
	14.2 Studies of Wafer Bonding and Thinning	210
	14.3 Backside Processing	210
	14.4 Debonding and Cleaning	212
	References	213
	15 Thinning, Via Reveal, and Backside Processing – Overview	215
	15.1 Introduction	215
	15.2 Wafer Edge Trimming	216
	15.3 Thin Wafer Support Systems	218
	15.3.1 Glass Carrier Support System with Laser Debonding Approach	220
	15.3.2 Thermoplastic Glue Thin Wafer Support System – Thermal Slide Debondable System	220
	15.3.3 Room-Temperature, Peel-Debondable Thin Wafer Support Systems	221
	15.4 Wafer Thinning	222
	15.5 Thin Wafer Backside Processing	226
	15.5.1 Via-Middle Thin Wafer Backside Processing: “Via-Reveal” Process	226
	15.5.1.1 Mechanical Via Reveal	226
	15.5.1.2 “Soft” Via Reveal	226
	15.5.2 Via-Last Thin Wafer Backside Processing	227
	References	229
	16 Backside Thinning and Stress-Relief Techniques for Thin Silicon Wafers	231
	16.1 Introduction	231
	16.2 Thin Semiconductor Devices	231
	16.3 Wafer Thinning Techniques	232
	16.3.1 Wafer Grinding	233
	16.3.2 Wet-Chemical Spin Etching	234
	16.3.3 CMP Polishing	235
	16.3.4 Plasma Dry Etching	236
	16.3.5 Dry Polish	237
	16.3.6 Chemical–Mechanical Grinding (CMG)	238
	16.4 Fracture Tests for Thin Silicon Wafers	238
	16.5 Comparison of Stress-Relief Techniques for Wafer Backside Thinning	240
	16.6 Process Flow for Wafer Thinning and Dicing	244
	16.7 Summary and Outlook on 3D Integration	246
	References	247
	17 Via Reveal and Backside Processing	251
	17.1 Introduction	251
	17.2 Via Reveal and Backside Processing in Via-Middle Process	251
	17.3 Backside Processing in Back-Via Process	256
	17.4 Backside Processing and Impurity Gettering	258
	17.5 Backside Processing for RDL Formation	261
	References	263
	18 Dicing, Grinding, and Polishing (Kiru Kezuru and Migaku)	265
	18.1 Introduction	265
	18.2 Grinding and Polishing	265
	18.2.1 Grinding General	265
	18.2.1.1 Grinding Method	265
	18.2.1.2 Rough Grinding and Fine Grinding	266
	18.2.1.3 The Grinder Polisher	267
	18.2.2 Thinning	267
	18.2.2.1 Stress Relief	269
	18.2.2.2 Die Attach Film	270
	18.2.2.3 All-in-One System	270
	18.2.2.4 Dicing Before Grinding	270
	18.2.3 Grinding Topics for 3DIC Such as TSV Devices	270
	18.2.3.1 Wafer Support System	270
	18.2.3.2 Edge Trimming	271
	18.2.3.3 Grinding to Improve Flatness	272
	18.2.3.4 Higher Level of Cleanliness	272
	18.2.3.5 Via Reveal	273
	18.2.3.6 Planarization	273
	18.3 Dicing	274
	18.3.1 Blade Dicing General	274
	18.3.1.1 Dicing Method	274
	18.3.1.2 Blade Dicing Point	274
	18.3.1.3 Blade	275
	18.3.1.4 Optimization of Process Control	276
	18.3.1.5 Dicer	276
	18.3.1.6 Dual Dicing Applications	276
	18.3.2 Thin Wafer Dicing	277
	18.3.3 Low-k Dicing	278
	18.3.4 Other Laser Dicing	278
	18.3.4.1 Ablation	278
	18.3.4.2 Laser Full Cut Application	279
	18.3.4.3 Stealth Dicing (SD)	280
	18.3.5 Dicing Topics for 3D-IC Such as TSV	281
	18.3.5.1 Cutting of Chip on Chip (CoC) and Chip on Wafer (CoW)	282
	18.3.5.2 Singulation of CoW and Wafer on Wafer (WoW)	283
	18.4 Summary	284
	Further Reading	284
	19 Overview of Bonding and Assembly for 3D Integration	285
	19.1 Introduction	285
	19.2 Direct, Indirect, and Hybrid Bonding	286
	19.3 Requirements for Bonding Process and Materials	287
	19.4 Bonding Quality Characterization	291
	19.5 Discussion of Specific Bonding and Assembly Technologies	293
	19.6 Summary and Conclusions	297
	References	298
	20 Bonding and Assembly at TSMC	303
	20.1 Introduction	303
	20.2 Process Flow	304
	20.3 Chip-on-Wafer Stacking	305
	20.4 CoW-on-Substrate (CoWoS) Stacking	307
	20.5 CoWoS Versus CoCoS	307
	20.6 Testing and Known Good Stacks (KGS)	308
	20.7 Future Perspectives	309
	References	309
	21 TSV Packaging Development at STATS ChipPAC	311
	21.1 Introduction	311
	21.2 Development of the 3DTSV Solution for Mobile Platforms	313
	21.3 Alternative Approaches and Future Developments	317
	References	318
	22 Cu–SiO2 Hybrid Bonding	319
	22.1 Introduction	319
	22.2 Blanket Cu–SiO2 Direct Bonding Principle	320
	22.2.1 Chemical–Mechanical Polishing Parameters	320
	22.3 Aligned Bonding	323
	22.3.1 Wafer-to-Wafer Bonding	323
	22.3.2 Die-to-Wafer Bonding in Pick-and-Place Equipment	323
	22.3.3 Die-to-Wafer by the Self-Assembly Technique	324
	22.4 Blanket Metal Direct Bonding Principle	326
	22.5 Electrical Characterization	328
	22.5.1 Wafer-to-Wafer and Die-to-Wafer Copper-Bonding Electrical Characterization	328
	22.5.2 Reliability	331
	22.5.3 Thermal Cycling	331
	22.5.4 Stress Voiding (SIV) Test on 200° C Postbonding Annealed Samples	332
	22.5.5 Package-Level Electromigration Test	333
	22.6 Conclusions	334
	References	335
	23 Bump Interconnect for 2.5D and 3D Integration	337
	23.1 History	337
	23.2 C4 Solder Bumps	339
	23.3 Copper Pillar Bumps	340
	23.4 Cu Bumps	343
	23.5 Electromigration	344
	References	346
	24 Self-Assembly Based 3D and Heterointegration	349
	24.1 Introduction	349
	24.2 Self-Assembly Process	349
	24.3 Key Parameters of Self-Assembly on Alignment Accuracies	351
	24.4 How to Interconnect Self-Assembled Chips to Chips or Wafers	352
	24.4.1 Flip-Chip-to-Wafer 3D Integration	353
	24.4.2 Reconfigured-Wafer-to-Wafer 3D Integration	355
	References	356
	25 High-Accuracy Self-Alignment of Thin Silicon Dies on Plasma-Programmed Surfaces	359
	25.1 Introduction	359
	25.2 Principle of Fluidic Self-Alignment Process for Thin Dies	359
	25.3 Plasma Programming of the Surface	360
	25.4 Preparation of Materials for Self-Alignment Experiments	361
	25.5 Self-Alignment Experiments	362
	25.6 Results of Self-Alignment Experiments	363
	25.7 Discussion	365
	25.8 Conclusions	366
	References	367
	26 Challenges in 3D Fabrication	369
	26.1 Introduction	369
	26.2 High-Volume Manufacturing for 3D Integration	370
	26.3 Technology Challenges	370
	26.4 Front-Side and Backside Wafer Processes	370
	26.5 Bonding and Underfills	374
	26.6 Multitier Stacking	376
	26.7 Wafer Thinning and Thin Die and Wafer Handling	377
	26.8 Strata Packaging and Assembly	380
	26.9 Yield Management	383
	26.10 Reliability	384
	26.11 Cost Management	386
	26.12 Future Perspectives	386
	References	388
	27 Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices	389
	27.1 Introduction	389
	27.2 Cu Stress in TSV	389
	27.3 Mitigation of Cu Pumping	392
	27.4 Impact of TSVs on FEOL Devices	395
	References	402
	28 Implications of Stress/Strain and Metal Contamination on Thinned Die	403
	28.1 Introduction	403
	28.2 Impacts of Cu Contamination on Device Reliabilities in Thinned 3DLSI	403
	28.3 Impacts of Local Stress and Strain on Device Reliabilities in Thinned 3DLSI	410
	28.3.1 Microbump-Induced Stresses in Stacked LSIs	411
	28.3.2 Microbump-Induced TMS in LSI	412
	28.3.3 Microbump-Induced LMS	413
	References	415
	29 Metrology Needs for 2.5D/3D Interconnects	417
	29.1 Introduction: 2.5D and 3D Reference Flows	417
	29.2 TSV Formation	418
	29.2.1 TSV Etch Metrology	419
	29.2.2 Liner, Barrier, and Seed Metrology	421
	29.2.3 Copper Fill Metrology (TSV Voids)	423
	29.2.4 Cross-Sectional SEM (Focused Ion Beam Milling Sample Preparation)	424
	29.2.5 X-Ray Microscopy and CT Inspection	424
	29.2.6 Stress Metrology in Cu and Si	426
	29.3 MEOL Metrology	428
	29.3.1 Edge Trim Inspection	429
	29.3.2 Bond Voids and Bond Strength Metrology	430
	29.3.2.1 Acoustic Microscopy: Operation	431
	29.3.2.2 Acoustic Microscopy for Defect Inspection and Review	431
	29.3.2.3 Other Bond Void Detection Techniques	432
	29.3.3 Bond Strength Metrology	433
	29.3.4 Bonded Wafer Thickness, Bow, and Warp	434
	29.3.4.1 Chromatic White Light	435
	29.3.4.2 Infrared Interferometry	436
	29.3.4.3 White Light Interferometry (or Coherence Scanning Interferometry)	438
	29.3.4.4 Laser Profiling	439
	29.3.4.5 Capacitance Probes	439
	29.3.4.6 Differential Backpressure Metrology	441
	29.3.4.7 Acoustic Microscopy for Measuring Bonded Wafer Thickness	441
	29.3.5 TSV Reveal Metrology	442
	29.4 Assembly and Packaging Metrology	444
	29.4.1 Wafer-Level C4 Bump and Microbump Metrology and Inspection	445
	29.4.2 Package-Level Inspection: Scanning Acoustic Microscopy	446
	29.4.3 Package-Level Inspection: X-Rays	448
	29.5 Summary	450
	References	451
	Index	455